Lead Digital Verification Engineer

Implant     ·      Fremont, CA     ·      Full time

We are looking for our first Lead Design Verification Engineer with strong CPU, ASIC design and verification fundamentals to work in Neuralink’s System-on-Chip (SoC) department under the Implant Team. This position offers a rare and unique opportunity to have a high impact in realizing state-of-the-art brain-computer interfaces as the first Verification Engineer on the SoC team. The SoC team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP). We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

About you:

• You find large challenges exciting and enjoy discovering and defining problems as much as solving them.
• You deliver. You may enjoy thoughtful conversations about problems and perfecting designs, but in the end, you know that what matters is delivering a manufacturable solution that works every time.
• You are a cross-disciplinary team member. You are excited to work with and learn from software, mechanical, electrical, materials, biological engineers, and neuroscientists. You are comfortable communicating across teams.
• Resourceful, flexible and adaptable; no task is too big or too small.

Key qualifications:

• Minimum 4-5 years of experience in digital ASIC verification.
• Excellence in SystemVerilog.
• Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell
• Experience with code coverage and regression setup.

Preferred qualifications:

• Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools.
• Experience on building test benches, testing, and debugging for a complex system-on-chip.
• Experience in formal verification.
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.
• Experience with IEEE-1801 (UPF) based design simulation flows
• Experience with low power gate level simulations
• Exposure with low power formal verification flows
• Strong hands-on experience in verification methodologies such as UVM
• Knowledge of ARM/RISC-V processor, AMBA bus
• Knowledge of power aware verification
• Experience with FPGA/emulation
• Experience with lab system bring up, writing diagnostic, and lab debugging

What we offer:

• An opportunity to change the world and work with some of the smartest and the most talented experts from different fields. 
• Growth potential. We rapidly advance team members who have an outsized impact. 
• Excellent medical, dental, and vision insurance through a PPO plan; parental leave.
• Flexible time off + paid holidays.
• Equity + 401(k) plan.
• Commuter Benefits.
• Meals provided.

Neuralink provides equal opportunity in all of our employment practices to all qualified employees and applicants without regard to race, color, religion, gender, national origin, age, disability, marital status, military status, genetic information or any other category protected by federal, state and local laws.  This policy applies to all aspects of the employment relationship, including recruitment, hiring, compensation, promotion, transfer, disciplinary action, layoff, return from layoff, training and social, and recreational programs. All such employment decisions will be made without unlawfully discriminating on any prohibited basis.

Multiple studies have found that a higher percentage of women and BIPOC candidates won’t apply if they don’t meet every listed qualification. Neuralink values candidates of all backgrounds. If you find yourself excited by our mission but you don’t check every box in the description, we encourage you to apply anyway!