Kernel is developing the future of non-invasive Neural Interfaces to enable applications requiring high-fidelity neural data.  We are looking for a Design Verification Engineer to work with our ASIC and FPGA teams to develop, use, and maintain a robust test environment.  A successful candidate will have the tools to build and grow a world-class verification environment and a passion for detail.

 

 

• Build UVM-based testing environment to support directed and randomized testing.
• Develop verification requirements and appropriate test cases for unit and top-level testing and verification.
• Collaborate with architects and designers to determine critical tests and parameter spaces.
• Evaluate design verification coverage and develop plans for closing gaps.
• Provide detailed and meaningful feedback to design engineers to address detected bugs and failures.

 

• M.S. in Electrical Engineering or Computer Science with 7+ years of experience in ASIC/FPGA Design Verification
• Experience writing UVM testbenches and environments with a focus on constrained random stimuli and assertion-based methodologies.
• Knowledge of verification with both functional and gate-level netlists
• Proficiency in scripting languages. TCL required, additional experience in Perl, Python, Makefiles, and BASH scripting preferred.
• Experience generating behavioral models for abstraction of complex modules.
• Excellent verbal and written communication.

 

• Experience with continuous integration systems like Jenkins
• Mixed-Signal verification methodologies and testbench approaches
• Experience with lab test equipment and post-silicon debug

 

Please apply here.