Explore the impact of imec’s technology solutions on tomorrow’s Machine Learning and AI systems.

What you will do

Imec has a strong research program to enable 10-100X more energy efficient AI accelerators for Neural Networks, based in-memory computations, enabled by its extensive semiconductor process and circuit knowledge.

Changing the underlying technology for AI accelerators not only improves energy efficiency dramatically but will also call for novel system architectures, spanning from SSD and DRAM to the compute core architectures, potentially across multiple accelerator nodes.

• You will explore the power, performance and area (PPA) of dedicate Machine Learning and AI architectures to benchmark them in imec’s Machine Learning technology offering
• Teaming up with various experts inside imec, you will explore and benchmark design and architecture trade-offs for new technologies to enable compute-in-memory for machine learning, computational memories and building a flexible and programmable digital system around it.
• You will be responsible for:
  • Exploring novel chip and system architectures to enable technology development, leveraging imec’s computational memories;
  • Modeling and simulating new architectures to analyze critical trade-offs and bottlenecks. You abstract away the lower level details and capture the essential traits that will determine power and performance;
  • Interfacing with imec’s circuit and algorithm experts to understand requirements and constraints for computational memory arrays for machine learning;
  • Driving imec’s system view on AI accelerators built on top of its technology solutions;
  • Generating and securing IP;
  • Keeping up-to-date on recent developments in the field. You do this by studying literature and interacting with your colleagues.
• Use your circuit design and system-level integration skills to define the guidelines of the next generation technology solutions, supporting the imec semiconductor scaling roadmap.
• Be responsible for top-down design planning, specification development the integration of Analog-computing based Machine Learning accelerator, memory macro and digital logic at a block level.
• Implement Design-Technology Co-Optimization (DTCO) and System-Technology Co-Optimization (STCO) techniques for novel logic and memory device solutions pursued by imec research team.
• Interact with a team of top-notch talents in design and architecture for Machine Learning, next-generation memory and logic technology solutions.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. We offer an exciting 2-year position in a rapidly growing, multi-disciplinary team. This is your chance to define and help drive imec’s technology and architecture roadmap to build the AI technology of the near and far away future.

With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, ‘our corporate university’, we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive salary with many fringe benefits.

Who you are

• You have obtained a Master’s degree in Electronics Engineering, with at least 3 years of relevant industrial experience or a PhD in circuit design.
• We are looking for your good knowledge of synthesis and place and route tools to allow the evaluation of PPAC (power consumption, performance (speed), die area, and cost) post synthesis and post place and route.
• Knowledge of tools like Synopsys DC compiler, IC Compiler, Cadence RC compiler and SoC Encounter are required, as well as basic understanding of circuit design.
• You have a background of digital implementation and SoC architecture for one or more application domains (Mobile, Server, …) and can make specification for different parts of SoC in different market spaces
• You work in a structured, transparent and accurate way.
• You are a constructive team player and actively share experience and knowledge with colleagues.
• Your networking skills, creativity, persistence and passion for what you do are highly valued.
• We are looking for your excellent communication skills in English, as you will work in a multicultural team and closely with our partners.

Please click here to apply